1. Technical Field of the Invention
This invention pertains to an I/O bus to host bridge in a processor system. More particularly, it relates to a PCI/host bridge apparatus and method providing redundant link connections in support of multiple I/O hubs.
2. Background Art
A host bridge chip as defined by Peripheral Component Interconnect (PCI) Local Bus Specification provides an interconnect between an I/O subsystem and one or more processors in a processing system. (See PCI 2.2 spec: “PCI Local Bus Specification” Revision 2.2, Dated Dec. 18, 1998.)
A PCI host bridge provides an interconnect between an I/O subsystem and one or more processors in a processing system. A host bridge typically provides data buffering capabilities for transferring read and write data between the I/O subsystem and the processors. Read and write commands or transactions that originate on the PCI bus and are destined for system memory are typically referred to as DMAs.
A PCI host bridge may also provide a means for translating addresses from a PCI memory address space to a system memory address space. A host bridge chip may provide a hardware mechanism to fetch table entries from system memory which describe how to map PCI addresses into system memory addresses. The host bridge uses a table entry to determine the system memory location to which a DMA operation will be directed.
The prior art provides support for a host bridge talking to a processor complex through an I/O hub chip over communications links between the host bridge and an I/O hub chip. Redundant communications links are provided to prevent a failure of a single communications link from disrupting communication between a host bridge and I/O hub chip. These communications links can be connected in a ring configuration where multiple host bridge chips and I/O hub chips are connected to the ring. A host bridge is configured to communicate with only one I/O hub chip, however, and must be reconfigured if communications with another I/O hub chip is desired.
It is desirable for certain system configurations to provide the capability to dynamically communicate with other I/O hub chips from the host bridge chip. This configuration improves system reliability by allowing a second processor complex to access an I/O subsystem in the event of a failure of a first processor complex.
Various methods have been proposed and implemented to achieve high availability I/O systems. One such system, described in U.S. Pat. No. 5,682,512, couples several processing nodes together using cluster bridges. The processing nodes comprise a microprocessor, memory and I/O interconnected by a system bus, while the cluster bridges comprise address translation logic as well as interfaces to a processor node via the system bus and one or more other cluster bridges via point-to-point communication lines. The I/O bridges may be PCI-based. The address translation logic takes addresses that correspond to a global address map and remaps them to local addresses if such a mapping exists. The system structure at each node contains one or more processors, memory and I/O. This system does not use address translation during DMA operations when moving from an I/O address space to a system memory address, does not dynamically route DMA operations to a desired processing node, and does not dynamically route interrupts to a desired processor by reusing a portion of the address translation mechanism.
It is an object of the invention to provide an improved I/O system and method.
It is a further object of the invention to provide a cost-effective way of building high availability I/O systems with a high degree of design reuse.
It is a further object of the invention to provide a method for using existing packet-based technology for redundant link connections and extending it to support dynamic access to multiple I/O hubs.
It is an object of the invention to provide access to translation table information residing in one processor complex while transferring data to another processor complex using the translation table information from that other complex.
It is a further object of the invention to provide subdivided PCI address space to determine from which processor complex to fetch translation table information.
It is a further object of the invention to provide dynamic routing of PCI interrupts from a particular PCI bus to different processor complexes (sometimes referred to as I/O hubs).
It is a further object of the invention to provide a system coherency protocol by which coherency is assured for cached translation table information and DMA read data originating from multiple processor complexes.